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(parent: 9d63f17) | patch
spi-nor: intel-spi: Check transfer length in the HW/SW cycle
authorBin Meng <bmeng.cn@gmail.com>
Mon, 11 Sep 2017 09:41:54 +0000 (02:41 -0700)
committerCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Wed, 11 Oct 2017 07:43:13 +0000 (09:43 +0200)
commitdb2ce7f3c7b01a6a3611fb8e0bfa453dec168a47
treedf5ef4a1c38c78ed37576ff6813cd19e9ccfd137tree | snapshot
parent9d63f17661e25fd28714dac94bdebc4ff5b75f09commit | diff
spi-nor: intel-spi: Check transfer length in the HW/SW cycle

Intel SPI controller only has a 64 bytes FIFO. This adds a sanity
check before triggering any HW/SW sequencer work.

Additionally for the SW sequencer, if given data length is zero,
we should not mark the 'Data Cycle' bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
drivers/mtd/spi-nor/intel-spi.c diff | blob | history
Domain: System / Kernel;