RS6000 Add 128-bit Binary Integer sign extend operations

RS6000 Add 128-bit Binary Integer sign extend operations

This patch adds the 128-bit sign extension instruction support and
corresponding builtin support.

RS6000 Add 128-bit Binary Integer sign extend operations

2021-06-08  Carl Love  <cel@us.ibm.com>

gcc/ChangeLog

	* config/rs6000/altivec.h (vec_signextll, vec_signexti, vec_signextq):
	Add define for new builtins.
	* config/rs6000/altivec.md(altivec_vreveti2): Add define_expand.
	* config/rs6000/rs6000-builtin.def (VSIGNEXTI, VSIGNEXTLL):  Add
	overloaded builtin definitions.
	(VSIGNEXTSB2W, VSIGNEXTSH2W, VSIGNEXTSB2D, VSIGNEXTSH2D,VSIGNEXTSW2D,
	VSIGNEXTSD2Q):	Add builtin expansions.
	(SIGNEXT): Add P10 overload definition.
	* config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_VSIGNEXTI, P9V_BUILTIN_VEC_VSIGNEXTLL,
	P10_BUILTIN_VEC_SIGNEXT): Add overloaded argument definitions.
	* config/rs6000/vsx.md (vsx_sign_extend_v2di_v1ti): Add define_insn.
	(vsignextend_v2di_v1ti, vsignextend_qi_<mode>, vsignextend_hi_<mode>,
	vsignextend_si_v2di)[VIlong]: Add define_expand.
	Make define_insn vsx_sign_extend_si_v2di visible.
	* doc/extend.texi:  Add documentation for the vec_signexti,
	vec_signextll builtins and vec_signextq.

gcc/testsuite/ChangeLog

	* gcc.target/powerpc/int_128bit-runnable.c (extsd2q): Update expected
	count.
	Add tests for vec_signextq.
	* gcc.target/powerpc/p9-sign_extend-runnable.c:  New test case.