perf/x86/intel/uncore: Add Sapphire Rapids server UPI support
authorKan Liang <kan.liang@linux.intel.com>
Wed, 30 Jun 2021 21:08:33 +0000 (14:08 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Fri, 2 Jul 2021 13:58:39 +0000 (15:58 +0200)
commitda5a9156cd2a3be2b00f8defb529ee3e35e5769b
treebcbadc5d7dd802f839bd692f012c4b63e0a832ec
parentf57191edaaeb01279a88ace1be5b7230bdd8c0ab
perf/x86/intel/uncore: Add Sapphire Rapids server UPI support

Sapphire Rapids uses a coherent interconnect for scaling to multiple
sockets known as Intel UPI. Intel UPI technology provides a cache
coherent socket to socket external communication interface between
processors.

The layout of the control registers for a UPI uncore unit is similar to
a M2M uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-10-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/uncore_snbep.c