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[AArch64] optimise v4f16 fcmps to utilise vector instructions
authorCarey Williams <carey.williams@arm.com>
Mon, 22 Jan 2018 14:16:11 +0000 (14:16 +0000)
committerCarey Williams <carey.williams@arm.com>
Mon, 22 Jan 2018 14:16:11 +0000 (14:16 +0000)
commitda15b5b1161b7f290f2b3cb30db7d6bc06fb83fb
tree1a8afdba00241f67b91448ab63dd90dcc4c93ce5tree | snapshot
parent28d8a49f4276467e41ceec525b1cb2648f0ae653commit | diff
[AArch64] optimise v4f16 fcmps to utilise vector instructions

Improves the code generation for v4f16 FCMP instructions when FullFP16 is not supported.
Generating FCTVL(s) rather than a longer series of FCVTs.

Differential Revision: https://reviews.llvm.org/D41772

llvm-svn: 323118
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll diff | blob | history
Domain: System / Toolchain;