Cleanup some xarch emit logic (#85536)

Cleanup some xarch emit logic (#85536)

* Ensure floating-point codegen uses the VEX aware path

* Fix `IF_RRW_RRW_CNS` to be `IF_RWR_RRD_CNS`

* Fixup emitfmtsxarch.h to have a more consistent layout

* Allow querying the scheduling info for an insFormat

* Ensure the new insFormats are handled

* Ensure we consistently use `emitInsModeFormat`

* Ensure instructions which write to a mask register are EVEX only

* Improve REX.W handling for EVEX only instructions

* Ensure that instructions use the right update mode and tuple type

* Apply formatting patch

* Ensure DstSrcSrc is still handled correctly

* Ensure BLSI/BLSR are still handled in emitOutputAM

* Use static_assert_no_msg

* Fixing the disassembly for IF_RRW_SHF

* Fixing the IF check for shld/shrd on x86

* Use the correct name: inst_RV_TT_IV

* Ensure the 4 operand insFormats include the necessary constant

* Resolve an insFormat check on x86

* Ensure other SIMD code paths are VEX aware

* Improve throughput by using a less expensive emitSizeOfInsDsc

* Apply formatting patch

* Ensure emitSizeOfInsDsc_CNS is used for RWR_RRD_*RD_CNS

* Ensure genSimd12UpperClear uses `andps` for the pre-SSE4.1 path