arm64: Work around Falkor erratum 1009
authorChristopher Covington <cov@codeaurora.org>
Tue, 31 Jan 2017 17:50:19 +0000 (12:50 -0500)
committerWill Deacon <will.deacon@arm.com>
Wed, 1 Feb 2017 15:41:50 +0000 (15:41 +0000)
commitd9ff80f83ecbf4cbdf56d32d01c312498e4fb1cd
tree94f9560be4f1c75dd6300b4efcd1f278bf546755
parentec663d967b2276448a416406ca59ff247c0c80c5
arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain,
Falkor may prematurely complete the DSB before all loads and stores using
the old translation are observed. Instruction fetches are not subject to
the conditions of this erratum. If the original code sequence includes
multiple TLB invalidate instructions followed by a single DSB, onle one of
the TLB instructions needs to be repeated to work around this erratum.
While the erratum only applies to cases in which the TLBI specifies the
inner-shareable domain (*IS form of TLBI) and the DSB is ISH form or
stronger (OSH, SYS), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.

Based on work by Shanker Donthineni <shankerd@codeaurora.org>

Signed-off-by: Christopher Covington <cov@codeaurora.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Documentation/arm64/silicon-errata.txt
arch/arm64/Kconfig
arch/arm64/include/asm/cpucaps.h
arch/arm64/include/asm/tlbflush.h
arch/arm64/kernel/cpu_errata.c