V4 JIT: parameterize the prologue and epilogue generation
authorErik Verbruggen <erik.verbruggen@digia.com>
Tue, 12 Aug 2014 07:40:11 +0000 (09:40 +0200)
committerErik Verbruggen <erik.verbruggen@digia.com>
Thu, 14 Aug 2014 13:27:51 +0000 (15:27 +0200)
commitd9f33ccdef985badc56fd8940373748626beffc7
treeccacfa93345abba1d274dfb0bae178e855efb613
parent17743ea6e22535bd5c6c01436c40084f0c4053bc
V4 JIT: parameterize the prologue and epilogue generation

... with the regular (non-FP) registers that need to be saved. This
patch shouldn't change any of the JIT generated code, because all
regular callee saved registers are passed in.

Change-Id: Id11b8f37f06d80e8015ac6f0d0ccefdfa3342cbe
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
src/qml/jit/qv4assembler.cpp
src/qml/jit/qv4assembler_p.h
src/qml/jit/qv4isel_masm.cpp
src/qml/jit/qv4isel_masm_p.h
src/qml/jit/qv4registerinfo_p.h
src/qml/jit/qv4targetplatform_p.h