[AMDGPU][GFX9][DOC][NFC] Update assembler syntax description
authorDmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com>
Tue, 13 Dec 2022 11:01:17 +0000 (14:01 +0300)
committerDmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com>
Tue, 13 Dec 2022 11:01:17 +0000 (14:01 +0300)
commitd8ac03f15e81517c19a2a07d078b24498ec23380
tree62d85f98f4aea46d1e3cb32a24c7d2aba91eb4c1
parent564d47db9eb031ae1269f66311f6cb0c47153d1d
[AMDGPU][GFX9][DOC][NFC] Update assembler syntax description

Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469).
- Enable abs and neg modifiers for v_cndmask_b32 (https://reviews.llvm.org/D135900).
- Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet).
- Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783).
- Enable image_gather4h (https://reviews.llvm.org/D130764).
- Minor corrections and improvements.
34 files changed:
llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
llvm/docs/AMDGPU/gfx9_hwreg.rst
llvm/docs/AMDGPU/gfx9_imask.rst
llvm/docs/AMDGPU/gfx9_imm16_0533c2.rst [moved from llvm/docs/AMDGPU/gfx9_imm16_a04fb3.rst with 83% similarity]
llvm/docs/AMDGPU/gfx9_imm16_169952.rst [moved from llvm/docs/AMDGPU/gfx9_imm16_73139a.rst with 84% similarity]
llvm/docs/AMDGPU/gfx9_label.rst
llvm/docs/AMDGPU/gfx9_m_28b494.rst [moved from llvm/docs/AMDGPU/gfx9_m_254bcb.rst with 70% similarity]
llvm/docs/AMDGPU/gfx9_m_c141fc.rst [moved from llvm/docs/AMDGPU/gfx9_m_f5d306.rst with 78% similarity]
llvm/docs/AMDGPU/gfx9_msg.rst
llvm/docs/AMDGPU/gfx9_sbase_b0aa25.rst [moved from llvm/docs/AMDGPU/gfx9_sbase_010ce0.rst with 83% similarity]
llvm/docs/AMDGPU/gfx9_sdata_45d924.rst [moved from llvm/docs/AMDGPU/gfx9_sdata_eb6f2a.rst with 87% similarity]
llvm/docs/AMDGPU/gfx9_sdata_ba98a3.rst [moved from llvm/docs/AMDGPU/gfx9_sdata_aefe00.rst with 86% similarity]
llvm/docs/AMDGPU/gfx9_sdata_c1aec6.rst [moved from llvm/docs/AMDGPU/gfx9_sdata_c6aec1.rst with 84% similarity]
llvm/docs/AMDGPU/gfx9_soffset_02ec85.rst [moved from llvm/docs/AMDGPU/gfx9_soffset_ba92ce.rst with 84% similarity]
llvm/docs/AMDGPU/gfx9_srsrc_80eef6.rst [moved from llvm/docs/AMDGPU/gfx9_srsrc_e73d16.rst with 74% similarity]
llvm/docs/AMDGPU/gfx9_tgt.rst
llvm/docs/AMDGPU/gfx9_type_deviation.rst
llvm/docs/AMDGPU/gfx9_vaddr_cc213c.rst [moved from llvm/docs/AMDGPU/gfx9_vaddr_5d0b42.rst with 52% similarity]
llvm/docs/AMDGPU/gfx9_vdata_21b58d.rst [moved from llvm/docs/AMDGPU/gfx9_vdata_15d255.rst with 81% similarity]
llvm/docs/AMDGPU/gfx9_vdata_2d6239.rst [moved from llvm/docs/AMDGPU/gfx9_vdata_890652.rst with 83% similarity]
llvm/docs/AMDGPU/gfx9_vdata_4b260e.rst [moved from llvm/docs/AMDGPU/gfx9_vdata_16d321.rst with 83% similarity]
llvm/docs/AMDGPU/gfx9_vdata_84fab6.rst [moved from llvm/docs/AMDGPU/gfx9_vdata_a9ff5a.rst with 84% similarity]
llvm/docs/AMDGPU/gfx9_vdata_aa5a53.rst [moved from llvm/docs/AMDGPU/gfx9_vdata_35851e.rst with 84% similarity]
llvm/docs/AMDGPU/gfx9_vdata_ad559c.rst [moved from llvm/docs/AMDGPU/gfx9_vdata_0aba12.rst with 83% similarity]
llvm/docs/AMDGPU/gfx9_vdst_5d50a1.rst [moved from llvm/docs/AMDGPU/gfx9_vdst_322561.rst with 71% similarity]
llvm/docs/AMDGPU/gfx9_vdst_5ec176.rst [moved from llvm/docs/AMDGPU/gfx9_vdst_2ea017.rst with 77% similarity]
llvm/docs/AMDGPU/gfx9_vdst_875645.rst [new file with mode: 0644]
llvm/docs/AMDGPU/gfx9_vdst_a49b76.rst [new file with mode: 0644]
llvm/docs/AMDGPU/gfx9_vdst_d7c57e.rst [new file with mode: 0644]
llvm/docs/AMDGPU/gfx9_vdst_dfa6da.rst [moved from llvm/docs/AMDGPU/gfx9_vdst_3d7dcf.rst with 87% similarity]
llvm/docs/AMDGPU/gfx9_vdst_eae4c8.rst [moved from llvm/docs/AMDGPU/gfx9_vdst_473a69.rst with 78% similarity]
llvm/docs/AMDGPU/gfx9_vdst_f47754.rst [new file with mode: 0644]
llvm/docs/AMDGPU/gfx9_vsrc_ba3116.rst [moved from llvm/docs/AMDGPU/gfx9_vsrc_533a4e.rst with 79% similarity]
llvm/docs/AMDGPU/gfx9_waitcnt.rst