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(parent: 5a6b184) | patch
clk: tegra: Bump SCLK clock rate to 216 MHz
authorDmitry Osipenko <digetx@gmail.com>
Tue, 3 Oct 2017 23:02:41 +0000 (02:02 +0300)
committerThierry Reding <treding@nvidia.com>
Wed, 1 Nov 2017 14:00:05 +0000 (15:00 +0100)
commitd80a32fe98b7ce428669b774c3d10ecae3bc6e6d
tree03e39fd10340e1a04c7be43a91b0098bf7a30c51tree | snapshot
parent5a6b184a36b8f5ff01ce93c9251996e4f96310d7commit | diff
clk: tegra: Bump SCLK clock rate to 216 MHz

AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | history
Domain: System / Kernel;