[CPUFREQ] speedstep-centrino should ignore upper performance control bits
authorGary Hade <garyhade@us.ibm.com>
Mon, 6 Nov 2006 23:39:23 +0000 (15:39 -0800)
committerDave Jones <davej@redhat.com>
Wed, 8 Nov 2006 22:14:30 +0000 (17:14 -0500)
commitd7a1944e8da5e91859b98259189aaaa4d8b7fa07
tree78741c84c14e8f53ed624811911766d29ab76013
parent4e74663c5d7eefc1f953b9b0bdacab09917b4eac
[CPUFREQ] speedstep-centrino should ignore upper performance control bits

On some systems such as the IBM x3650 there are bits set in the
upper half of the control values provided by the _PSS object.
These bits are only relevant for cpufreq drivers that use IO ports
which are not currently supported by the speedstep-centrino driver.
The current MSR oriented code assumes that upper bits are not set
and thus fails to work correctly when they are.  e.g. the control
and status value equality check fails even though the ACPI spec
allows the inequality.

Signed-off-by: Gary Hade <garyh@us.ibm.com>
Signed-off-by: Dave Jones <davej@redhat.com>
arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c