drm/i915: Extract VESA DSC bpp alignment to separate function
authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Wed, 23 Nov 2022 10:05:51 +0000 (12:05 +0200)
committerStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Tue, 13 Dec 2022 16:17:52 +0000 (18:17 +0200)
commitd797f67d1e2568b152ee1af2334b11c1a48e5594
treeffe357f46ef15c69dc388b702bbfad8b174e7b97
parentd51f25eb479aeb61c194089f66261be67ff9237a
drm/i915: Extract VESA DSC bpp alignment to separate function

We might to use that function separately from intel_dp_dsc_compute_config
for DP DSC over MST case, because allocating bandwidth in that
case can be a bit more tricky. So in order to avoid code copy-pasta
lets extract this to separate function and reuse it for both SST
and MST cases.

v2: Removed multiple blank lines
v3: Rename intel_dp_dsc_nearest_vesa_bpp to intel_dp_dsc_nearest_valid_bpp
    to reflect its meaning more properly.
    (Manasi Navare)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221123100551.29080-1-stanislav.lisovskiy@intel.com
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/display/intel_dp.h
drivers/gpu/drm/i915/display/intel_dp_mst.c