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author	Andrew Savonichev <andrew.savonichev@gmail.com>
	Tue, 29 Dec 2020 16:49:09 +0000 (19:49 +0300)
committer	Andrew Savonichev <andrew.savonichev@gmail.com>
	Thu, 4 Mar 2021 11:08:19 +0000 (14:08 +0300)
commit	d791695cb5172b527e1b0717458d8852abcf34d1
tree	d483cd6ed35fd509a1577fd1c0feab2c62d5474a	tree \| snapshot
parent	1584e55a2602cd9fe0db059b06a217822ffac7cd	commit \| diff

[MCA] Add support for in-order CPUs

This patch adds a pipeline to support in-order CPUs such as ARM
Cortex-A55.

In-order pipeline implements a simplified version of Dispatch,
Scheduler and Execute stages as a single stage. Entry and Retire
stages are common for both in-order and out-of-order pipelines.

Differential Revision: https://reviews.llvm.org/D94928

28 files changed:

llvm/docs/CommandGuide/llvm-mca.rst		diff \| blob \| history
llvm/docs/ReleaseNotes.rst		diff \| blob \| history
llvm/include/llvm/MC/MCSchedule.h		diff \| blob \| history
llvm/include/llvm/MCA/Context.h		diff \| blob \| history
llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h		diff \| blob \| history
llvm/include/llvm/MCA/HardwareUnits/RetireControlUnit.h		diff \| blob \| history
llvm/include/llvm/MCA/Instruction.h		diff \| blob \| history
llvm/include/llvm/MCA/Stages/InOrderIssueStage.h	[new file with mode: 0644]	blob
llvm/include/llvm/MCA/Stages/RetireStage.h		diff \| blob \| history
llvm/include/llvm/Target/TargetSchedule.td		diff \| blob \| history
llvm/lib/MCA/CMakeLists.txt		diff \| blob \| history
llvm/lib/MCA/Context.cpp		diff \| blob \| history
llvm/lib/MCA/HardwareUnits/RetireControlUnit.cpp		diff \| blob \| history
llvm/lib/MCA/InstrBuilder.cpp		diff \| blob \| history
llvm/lib/MCA/Stages/InOrderIssueStage.cpp	[new file with mode: 0644]	blob
llvm/lib/MCA/Stages/RetireStage.cpp		diff \| blob \| history
llvm/lib/Target/AArch64/AArch64SchedA55.td		diff \| blob \| history
llvm/test/TableGen/InvalidMCSchedClassDesc.td		diff \| blob \| history
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/AArch64/Cortex/in-order-bottleneck-analysis.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s	[new file with mode: 0644]	blob
llvm/test/tools/llvm-mca/X86/in-order-cpu.s		diff \| blob \| history
llvm/tools/llvm-mca/llvm-mca.cpp		diff \| blob \| history
llvm/utils/TableGen/SubtargetEmitter.cpp		diff \| blob \| history

Domain: System / Toolchain;

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