powerpc/85xx: Add support for Integrated Flash Controller (IFC)
authorDipen Dudhat <Dipen.Dudhat@freescale.com>
Thu, 20 Jan 2011 10:59:35 +0000 (16:29 +0530)
committerKumar Gala <galak@kernel.crashing.org>
Mon, 4 Apr 2011 14:24:40 +0000 (09:24 -0500)
commitd789b5f5bc18199fe617878efaa32756f481e7c8
tree36ee9ef6d5bd64af6cdb373d221ef0bd85947e0f
parent28747f9bb1623d8333c419ae679b914bcabd4836
powerpc/85xx: Add support for Integrated Flash Controller (IFC)

The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
        - Functional muxing of pins between NAND, NOR and GPCM
        - Support memory banks of size 64KByte to 4 GBytes
        - Write protection capability (only for NAND and NOR)
        - Provision of Software Reset
        - Flexible Timing programmability for every chip select
        - NAND Machine
                - x8/ x16 NAND Flash Interface
                - SLC and MLC NAND Flash devices support with
                  configurable
                  page sizes of upto 4KB
                - Internal SRAM of 9KB which is directly mapped and
                  availble at
                  boot time for NAND Boot
                - Configurable block size
                - Boot chip select (CS0) available at system reset
        - NOR Machine
                - Data bus width of 8/16/32
                - Compatible with asynchronous NOR Flash
                - Directly memory mapped
                - Supports address data multiplexed (ADM) NOR device
                - Boot chip select (CS0) available at system reset
        - GPCM Machine (NORMAL GPCM Mode)
                - Support for x8/16/32 bit device
                - Compatible with general purpose addressable device
                  e.g. SRAM, ROM
                - External clock is supported with programmable division
                  ratio
        - GPCM Machine (Generic ASIC Mode)
                - Support for x8/16/32 bit device
                - Address and Data are shared on I/O bus
                - Following Address and Data sequences can be supported
                  on I/O bus
                       - 32 bit I/O: AD
                       - 16 bit I/O: AADD
                       - 8 bit I/O : AAAADDDD
                - Configurable Even/Odd Parity on Address/Data bus
                  supported

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc8xxx/Makefile
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c [new file with mode: 0644]
arch/powerpc/include/asm/config.h
arch/powerpc/include/asm/fsl_ifc.h [new file with mode: 0644]
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/immap_85xx.h