drm/amd/display: Add DP 2.0 DCCG
authorFangzhi Zuo <Jerry.Zuo@amd.com>
Mon, 26 Jul 2021 18:23:42 +0000 (14:23 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Sep 2021 20:55:10 +0000 (16:55 -0400)
commitd76b12da98dfb5e0cb0b7c3709372632b87da2e6
tree47584eb0d095f846bcbbd89dbe4a399f9052b41f
parent3bc8d9214679cc4dbd1dee634bd98a5996adbcfb
drm/amd/display: Add DP 2.0 DCCG

HW Blocks:

        +--------+  +-----+  +------+
        |  OPTC  |  | HDA |  | HUBP |
        +--------+  +-----+  +------+
            |          |        |
            |          |        |
    HPO ====|==========|========|====
     |      |          v        |
     |      |       +-----+     |
     |      |       | APG |     |
     |      |       +-----+     |
     |      |          |        |
     |      v          v        v
     |     +---------------------+
     |     |  HPO Stream Encoder |
     |     +---------------------+
     |                 |
     |                 v
     |      +--------------------+
     |      |  HPO Link Encoder  |
     |      +--------------------+
     |                 |
     v  ===============|=============
                       v
              +------------------+
              |  DIO Output Mux  |
              +------------------+
                       |
                       v
                    +-----+
                    | PHY |
                    +-----+
                       | PHYD32CLK[0]
                       v
                    +------+
                    | DCCG |
                    +------+
                       |
                       v
                   SYMCLK32

Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h