i965/state: Create separate dirty state bits for each pipeline
authorJordan Justen <jordan.l.justen@intel.com>
Sun, 8 Mar 2015 07:21:46 +0000 (23:21 -0800)
committerJordan Justen <jordan.l.justen@intel.com>
Tue, 31 Mar 2015 23:40:24 +0000 (16:40 -0700)
commitd70f4e6daf4a548eb6debaa2a1646fea21e5fbf3
tree34cfad91ee6c4952e4da3716c751ff99389fe260
parentdb119550725d438c928c50382a2a675b37c24a66
i965/state: Create separate dirty state bits for each pipeline

When clearing the state for a pipeline, we will save changed state for
the other pipelines.

v3:
 * Adjust brw_upload_pipeline_state
   * Don't pull pipeline state bits into common state bits
   * Don't clear pipeline state bits
 * Adjust 'clear' phase
   * brw_clear_dirty_bits is now brw_render_state_finished
   * Move cross-pipeline state flagging to brw_pipeline_state_finished
   * Move pipeline clears to brw_pipeline_state_finished

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/brw_state_upload.c