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RISC-V: Add AIA related CSR defines
authorAnup Patel <apatel@ventanamicro.com>
Tue, 18 Jan 2022 05:42:40 +0000 (11:12 +0530)
committerAnup Patel <anup@brainfault.org>
Fri, 21 Apr 2023 12:15:39 +0000 (17:45 +0530)
commitd6f5f6e904be628941eeab7d6ae7d1fb9190c486
tree1e88572179a9b276fd30abbcce81765e8cf27f04tree | snapshot
parent90deec51d726b4d829ca7a684595154bebdf8353commit | diff
RISC-V: Add AIA related CSR defines

The RISC-V AIA specification improves handling per-HART local interrupts
in a backward compatible manner. This patch adds defines for new RISC-V
AIA CSRs.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/csr.h diff | blob | history
Domain: System / Kernel;