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Revert "[RISCV] Add sifive-x280 processor with all of its extensions"
authorMichael Maitland <michaeltmaitland@gmail.com>
Fri, 5 May 2023 15:17:41 +0000 (08:17 -0700)
committerMichael Maitland <michaeltmaitland@gmail.com>
Fri, 5 May 2023 15:20:18 +0000 (08:20 -0700)
commitd6bd4ea35437b1d39933e9526779e8c6e03125e0
tree15b7ca651ab63d3dc3a88bd4ccadf12c078c8725tree | snapshot
parentb33b000ac8ec339a795dc33f16213def54d13cf4commit | diff
Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

This commit causes tests to fail.

This reverts commit 55e196e7718c543b4492f2949c13de003a4ba443.
clang/test/Driver/riscv-cpus.c diff | blob | history
llvm/docs/ReleaseNotes.rst diff | blob | history
llvm/lib/Target/RISCV/RISCVProcessors.td diff | blob | history
Domain: System / Toolchain;