drm/i915: Use a cached mapping for the physical HWS
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 3 Sep 2018 15:23:04 +0000 (16:23 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 3 Sep 2018 16:55:59 +0000 (17:55 +0100)
commitd6acae363e63d655ba892c139ba14f24206462c0
treef92ecf6401109a9f619448ded1dd5f49e5567e8a
parenta0e731f4e26c4d774e71f9e69fff3e88d49dd34f
drm/i915: Use a cached mapping for the physical HWS

Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.

Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so far have not reoccurred with this patch. How reliable that
evidence is remains to be seen.

v2: Explicitly pass the expected physical address to the hw
v3: Also remember the wild writes we once had for HWS above 4G.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20180903152304.31589-2-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_engine_cs.c
drivers/gpu/drm/i915/intel_ringbuffer.c