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author	Simon Pilgrim <llvm-dev@redking.me.uk>
	Wed, 31 May 2023 14:33:44 +0000 (15:33 +0100)
committer	Simon Pilgrim <llvm-dev@redking.me.uk>
	Wed, 31 May 2023 15:39:09 +0000 (16:39 +0100)
commit	d6a36619cec44d02a2a3526eceb2ac128d90e030
tree	f6208f9ee82567dc51628fa16e0d3c95fca2dd83	tree \| snapshot
parent	f29f1c7e23d555c95a199f8e77fefe87e91664cf	commit \| diff

[X86] X86FixupVectorConstantsPass - use VBROADCASTSS/VBROADCASTSD for integer vector loads on AVX1-only targets

Matches behaviour in lowerBuildVectorAsBroadcast

127 files changed:

llvm/lib/Target/X86/X86FixupVectorConstants.cpp		diff \| blob \| history
llvm/test/CodeGen/X86/abdu-vector-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/abdu-vector-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx-logic.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx-shift.ll		diff \| blob \| history
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll		diff \| blob \| history
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-add.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-bitreverse.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-bitselect.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-pavg.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-pmuldq.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-sdiv.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-smax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-smin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-sub-usat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-udiv.ll		diff \| blob \| history
llvm/test/CodeGen/X86/combine-urem.ll		diff \| blob \| history
llvm/test/CodeGen/X86/concat-cast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/freeze-vector.ll		diff \| blob \| history
llvm/test/CodeGen/X86/gfni-funnel-shifts.ll		diff \| blob \| history
llvm/test/CodeGen/X86/gfni-rotates.ll		diff \| blob \| history
llvm/test/CodeGen/X86/gfni-shifts.ll		diff \| blob \| history
llvm/test/CodeGen/X86/horizontal-reduce-umax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/horizontal-reduce-umin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/i64-to-float.ll		diff \| blob \| history
llvm/test/CodeGen/X86/insert-into-constant-vector.ll		diff \| blob \| history
llvm/test/CodeGen/X86/masked_store_trunc.ll		diff \| blob \| history
llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/masked_store_trunc_usat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/midpoint-int-vec-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/midpoint-int-vec-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/paddus.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pmaddubsw.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr31773.ll		diff \| blob \| history
llvm/test/CodeGen/X86/psubus.ll		diff \| blob \| history
llvm/test/CodeGen/X86/sadd_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shrink_vmul.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shuffle-strided-with-offset-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/splat-for-size.ll		diff \| blob \| history
llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/ssub_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/uadd_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/umax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll		diff \| blob \| history
llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll		diff \| blob \| history
llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll		diff \| blob \| history
llvm/test/CodeGen/X86/usub_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/var-permute-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_anyext.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_cast3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_cmp_uint-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_int_to_fp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_minmax_uint.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_smulo.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_uaddo.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_umulo.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_usubo.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-bitreverse.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-blend.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-rot-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-rot-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-rot-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-rot-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-idiv.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-lzcnt-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-mul.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-popcnt-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-popcnt-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-umin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-rotate-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-rotate-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-ashr-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-ashr-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-lshr-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-shl-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-shl-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shuffle-combining.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-math.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-packus.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-ssat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc-usat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-trunc.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-tzcnt-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-tzcnt-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-unsigned-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vselect-avx.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vselect-minmax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vselect-pcmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/x86-interleaved-access.ll		diff \| blob \| history
llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll		diff \| blob \| history

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