[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
authorNirav Dave <niravd@google.com>
Wed, 13 Mar 2019 17:07:09 +0000 (17:07 +0000)
committerNirav Dave <niravd@google.com>
Wed, 13 Mar 2019 17:07:09 +0000 (17:07 +0000)
commitd6351340bb9bf7703fb79629efdba5886d434694
tree64e4d230eacfca1de147baf79d0665c3185d9ff7
parentbef4fe056dcc1fb95e4aa087b141f073955d8b3b
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.

Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.

CodeGen tests with non-reordering changes:

  X86/aligned-variadic.ll -- memory-based add folded into stored leaq
  value.

  X86/constant-combiners.ll -- Optimizes out overlap between stores.

  X86/pr40631_deadstore_elision -- folds constant byte store into
  preceding quad word constant store.

Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet

Reviewed By: courbet

Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59260

llvm-svn: 356068
52 files changed:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
llvm/test/CodeGen/AArch64/addr-of-ret-addr.ll
llvm/test/CodeGen/AArch64/alloca.ll
llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll
llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
llvm/test/CodeGen/AArch64/win64_vararg.ll
llvm/test/CodeGen/AMDGPU/call-argument-types.ll
llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
llvm/test/CodeGen/ARM/memset-inline.ll
llvm/test/CodeGen/ARM/thumb1_return_sequence.ll
llvm/test/CodeGen/ARM/unaligned_load_store.ll
llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
llvm/test/CodeGen/AVR/directmem.ll
llvm/test/CodeGen/BPF/undef.ll
llvm/test/CodeGen/MSP430/cc_args.ll
llvm/test/CodeGen/Mips/v2i16tof32.ll
llvm/test/CodeGen/PowerPC/f128-aggregates.ll
llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll
llvm/test/CodeGen/Thumb/frame-access.ll
llvm/test/CodeGen/Thumb/mvn.ll
llvm/test/CodeGen/X86/aligned-variadic.ll
llvm/test/CodeGen/X86/atomic-idempotent.ll
llvm/test/CodeGen/X86/avx-load-store.ll
llvm/test/CodeGen/X86/btc_bts_btr.ll
llvm/test/CodeGen/X86/combine-sbb.ll
llvm/test/CodeGen/X86/constant-combines.ll
llvm/test/CodeGen/X86/min-legal-vector-width.ll
llvm/test/CodeGen/X86/musttail-varargs.ll
llvm/test/CodeGen/X86/musttail.ll
llvm/test/CodeGen/X86/nosse-vector.ll
llvm/test/CodeGen/X86/oddshuffles.ll
llvm/test/CodeGen/X86/pr40631_deadstore_elision.ll
llvm/test/CodeGen/X86/rotate.ll
llvm/test/CodeGen/X86/rotate4.ll
llvm/test/CodeGen/X86/sadd_sat_vec.ll
llvm/test/CodeGen/X86/shift-and.ll
llvm/test/CodeGen/X86/shrink_vmul-widen.ll
llvm/test/CodeGen/X86/shrink_vmul.ll
llvm/test/CodeGen/X86/ssub_sat_vec.ll
llvm/test/CodeGen/X86/uadd_sat_vec.ll
llvm/test/CodeGen/X86/usub_sat_vec.ll
llvm/test/CodeGen/X86/vastart-defs-eflags.ll
llvm/test/CodeGen/X86/vec_fpext.ll
llvm/test/CodeGen/X86/widen_cast-2.ll
llvm/test/CodeGen/X86/widen_load-2.ll
llvm/test/CodeGen/X86/win64_frame.ll
llvm/test/CodeGen/X86/win64_vararg.ll
llvm/test/CodeGen/X86/x86-64-ms_abi-vararg.ll
llvm/test/CodeGen/XCore/byVal.ll