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(parent: ae6091d) | patch
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:09 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:35 +0000 (08:24 +0900)
commitd620614f3f28f18783d90035a1a5b1ec4f47f99b
tree54d2db52bd1d490e723e6d3c9ff990729370bb2dtree | snapshot
parentae6091ddf517d097c40fb4772369e1c3dcda09adcommit | diff
dt-bindings: clock: Add StarFive JH7110 PLL clock generator

Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;