[RISCV] Add vsseg intrinsic for fixed length vectors
authorLuke Lau <luke@igalia.com>
Wed, 1 Mar 2023 00:55:21 +0000 (00:55 +0000)
committerLuke Lau <luke@igalia.com>
Wed, 8 Mar 2023 17:19:03 +0000 (17:19 +0000)
commitd610c6c9c73576a8afb9831a0c6e8fc675c2a6e6
tree8f1e818d35443fac89d737ff88e1d66f28a407d3
parent0538bfe7744ad9a1a4b1ffe5aa5c6466f88aac8f
[RISCV] Add vsseg intrinsic for fixed length vectors

These intrinsics are equivalent to the regular @llvm.riscv.vssegNF
intrinsics, only they accept fixed length vectors in their overloaded
types: The regular intrinsics only operate on scalable vectors.
These intrinsics convert the fixed length vectors to scalable ones, and
then lower it on to the regular scalable intrinsic.

This mirrors the intrinsics added in 0803dba7dd998ad073d75a32b65296734c10ae70
This will be used in a later patch with the Interleaved Access pass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145022
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-store.ll [new file with mode: 0644]