[AArch64] Match pairwise add/fadd pattern
authorSanne Wouda <Sanne.Wouda@arm.com>
Sat, 12 Sep 2020 00:17:42 +0000 (01:17 +0100)
committerSanne Wouda <Sanne.Wouda@arm.com>
Thu, 17 Sep 2020 15:27:01 +0000 (16:27 +0100)
commitd5fd3d9b903ef6d96c6b3b82434dd0461faaba55
tree5b4b7f61fa02558c44ae5b38262114dcb71c9d70
parent3ee87a976d52a2379d007046f9a1ad4a07f440c0
[AArch64] Match pairwise add/fadd pattern

D75689 turns the faddp pattern into a shuffle with vector add.

Match this new pattern in target-specific DAG combine, rather than ISel,
because legalization (for v2f32) turns it into a bit of a mess.

- extended to cover f16, f32, f64 and i64
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/faddp-half.ll
llvm/test/CodeGen/AArch64/faddp.ll
llvm/test/CodeGen/AArch64/vecreduce-fadd.ll