projects / platform / kernel / linux-starfive.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2a29fe8) | patch
dt-bindings: clock: add Intel Agilex5 clock manager
authorNiravkumar L Rabara <niravkumar.l.rabara@intel.com>
Wed, 2 Aug 2023 02:58:42 +0000 (10:58 +0800)
committerDinh Nguyen <dinguyen@kernel.org>
Tue, 8 Aug 2023 11:32:34 +0000 (06:32 -0500)
commitd5f0942b5066e28138476259d076e4d6c871da7d
tree68593ece6a1c23a4fa710dec235a37f93f0b50eftree | snapshot
parent2a29fe831f80f6d9187e49a272d795f3d1b54cdbcommit | diff
dt-bindings: clock: add Intel Agilex5 clock manager

Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.

Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/intel,agilex5-clkmgr.h [new file with mode: 0644] blob
Domain: System / Kernel;