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(parent: 5f4e0be) | patch
clk: sunxi: add PLL5 and PLL6 support
authorEmilio López <emilio@elopez.com.ar>
Mon, 23 Dec 2013 03:32:37 +0000 (00:32 -0300)
committerEmilio López <emilio@elopez.com.ar>
Sat, 28 Dec 2013 20:08:17 +0000 (17:08 -0300)
commitd584c1331d6421e2387eab10b11fa6f08b4a4b5f
tree7c1d6a78ae45ac0aed61a96ae856f9cd295f70a3tree | snapshot
parent5f4e0be3a72325fbc4d349a847cc9b2edd85b6d2commit | diff
clk: sunxi: add PLL5 and PLL6 support

This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
Domain: System / Uncategorized;