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(parent: 8db2001) | patch
GlobalISel: Allow bitcount ops to have different result type
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 31 Jan 2019 02:09:57 +0000 (02:09 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 31 Jan 2019 02:09:57 +0000 (02:09 +0000)
commitd5684f76e099b18b972b7e3445adf168d7a116ef
tree54f4d0272f6f46bf1f36a297721a2954b60028batree | snapshot
parent8db2001d52444e8e24197dde160b8ad82ea1d7c9commit | diff
GlobalISel: Allow bitcount ops to have different result type

For AMDGPU the result is always 32-bit for 64-bit inputs.

llvm-svn: 352717
12 files changed:
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h diff | blob | history
llvm/include/llvm/Target/GenericOpcodes.td diff | blob | history
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/ARM/ARMLegalizerInfo.cpp diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir [new file with mode: 0644] blob
llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp diff | blob | history
Domain: System / Toolchain;