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[RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable...
authorCraig Topper <craig.topper@sifive.com>
Tue, 18 Jul 2023 16:50:30 +0000 (09:50 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 18 Jul 2023 17:04:33 +0000 (10:04 -0700)
commitd53d842d12ceb182f1f5c12cc001b09f9000dbf4
treef362af53607d9651e47f7331715a96c6d7649828tree | snapshot
parentca72457346071f807e375e71eb0612c7ac508507commit | diff
[RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector.

Before falling back to CreateCoercedStore, detect a scalable vector
return being coerced to fixed vector. Handle it using a vector.extract
intrinsic without going through memory.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D155495
clang/lib/CodeGen/CGCall.cpp diff | blob | history
clang/test/CodeGen/attr-arm-sve-vector-bits-call.c diff | blob | history
clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c diff | blob | history
Domain: System / Toolchain;