i965: use L3 data cache for SSBOs
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Mon, 26 Sep 2016 14:08:52 +0000 (15:08 +0100)
committerLionel Landwerlin <lionel.g.landwerlin@intel.com>
Wed, 5 Oct 2016 11:24:04 +0000 (12:24 +0100)
commitd51c1f9d51ef0e80873a9a32c48606cdce25a209
treea36f11f44b3d64a16581086cb84f80bf6eeaffdf
parenta40640f5303c9d03845459ecc364a3466d25cb5b
i965: use L3 data cache for SSBOs

Anv programs the hardware to use L3 data cache if we use either SSBOs or
images in the shaders, we can program i965 the same way.

gl_shader_program has a bit of a confusing named field with
'NumAtomicBuffers'. It doesn't tell how many buffers are accessed by the
shader in an atomic way but instead the number of atomic counters
manipulated by the shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
src/mesa/drivers/dri/i965/gen7_l3_state.c