[X86][Costmodel] Load/store i32/f32 Stride=6 VF=4 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:27:58 +0000 (16:27 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:58:57 +0000 (16:58 +0300)
commitd51532d8aad529fcefeedd686f0f1d2d967661f5
treea7dcdf3899e2855056b6625b1837afecab2fe314
parent764fd5f463e4a2d13e77751e0da1c623d2781d4b
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=4 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/szEj1ceee - for intels `Block RThroughput: =15.0`; for ryzens, `Block RThroughput: <=8.8`
So could pick cost of `15`.

For store we have:
https://godbolt.org/z/81bq4fTo1 - for intels `Block RThroughput: =12.0`; for ryzens, `Block RThroughput: <=10.0`
So we could pick cost of `12`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111087
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll