drm/i915/mtl: Cleanup usage of phy lane reset

drm/i915/mtl: Cleanup usage of phy lane reset

From PICA message bus we wait for acknowledgment from
read/write commands. In case of an error, we reset the
bus for the next command.

Current implementation ends up resetting message bus twice
in cases where error is not the timeout. Since, we only need
to reset message bus once, let's move reset to corresponding
timeout error and drop the excess reset function calls from
read/write functions.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609122130.69794-1-mika.kahola@intel.com