riscv: dts: microchip: add a devicetree for aries' m100pfsevp
authorConor Dooley <conor.dooley@microchip.com>
Tue, 27 Sep 2022 11:19:22 +0000 (12:19 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Tue, 27 Sep 2022 17:53:58 +0000 (18:53 +0100)
commitd49166646e44064b694a2e631fcdba4f814746d9
tree2d6a447154a959f4cfcbe7fdfeac1b27d4195896
parent978a17d1a688db025275d282665ab3f39407191d
riscv: dts: microchip: add a devicetree for aries' m100pfsevp

Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2GB DDR4 SDRAM dedicated to the HMS
- 512MB DDR4 SDRAM dedicated to the FPGA
- 32 MB SPI NOR Flash
- 4 GByte eMMC

and a carrier board with:
- 2x Gigabit Ethernet
- USB
- 2x UART
- 2x CAN
- TFT connector
- HSMC extension connector
- 3x PMOD extension connectors
- microSD-card slot

Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod
Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf
Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/microchip/Makefile
arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi [new file with mode: 0644]
arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts [new file with mode: 0644]