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[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
authorAlex Bradbury <asb@lowrisc.org>
Wed, 3 Oct 2018 11:14:26 +0000 (11:14 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Wed, 3 Oct 2018 11:14:26 +0000 (11:14 +0000)
commitd464ed8c2e4071fc79f213038e570b6319110a7d
tree042506f61eea1f885b1d1d9ab28aa129b5c2a937tree | snapshot
parenta9ac5994b1ec3b17639c755117c5c56fd40e3e8acommit | diff
[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td

1. brcond operates on an condition.
2. atomic_fence and the pseudo AMO instructions should all take xlen immediates

This allows the same definitions and patterns to work for RV64 (XLenVT==i64).

llvm-svn: 343678
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoA.td diff | blob | history
Domain: System / Toolchain;