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Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow"
authorPhilip Reames <preames@rivosinc.com>
Tue, 17 May 2022 22:51:41 +0000 (15:51 -0700)
committerPhilip Reames <preames@rivosinc.com>
Tue, 17 May 2022 22:53:13 +0000 (15:53 -0700)
commitd4545e6fa0366718c2416d3578dd4e1f26855c29
treed297a7909b34ac312a4149c477f25841d2ddf709tree | snapshot
parent996834e6813ab5481a58e42e7a11f57d243a3a99commit | diff
Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow"

This reverts commit 79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea.

The stronger asserts served their purpose; I stumbled across another bug.  Will reapply once this one is also fixed.

The bug appears to be a variant of a previous one:
* We mutate an instruction in one block.
* That mutation changes the phase3 results of another block.

This is very similiar to a previous issue, except cross block instead of within a single block.
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp diff | blob | history
Domain: System / Toolchain;