i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.
authorKenneth Graunke <kenneth@whitecape.org>
Wed, 12 Nov 2014 19:17:55 +0000 (11:17 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 5 Jan 2015 01:21:33 +0000 (17:21 -0800)
commitd41cf9fb60cc4f2183daa4fd58fad72bf7e75f85
treef0d240b6be39f2a73c74478eac66124986cdcc55
parent3793a1b42149112f543d33a622a163a5057ecc3d
i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.

According to the documentation, we need to do a CS stall on every fourth
PIPE_CONTROL command to avoid GPU hangs.  The kernel does a CS stall
between batches, so we only need to count the PIPE_CONTROLs in our batches.

v2: Get the generation check right (caught by Chris Wilson),
    combine the ++ with the check (suggested by Daniel Vetter).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/intel_batchbuffer.c