[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
authorManolis Tsamis <manolis.tsamis@vrull.eu>
Tue, 14 Feb 2023 18:43:00 +0000 (19:43 +0100)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 14 Feb 2023 19:25:47 +0000 (20:25 +0100)
commitd4012bc43f9a752d77f464286d91f72f4c6970ee
tree01ea11c7f9b99d9c570c2d15d2a8926b2d17f8a2
parent179db7efe567ed76e36b6c4d69605b426d8f70ca
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension

The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154

Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143847
15 files changed:
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/xtheadmac.ll [new file with mode: 0644]
llvm/test/MC/RISCV/rv32xtheadmac-invalid.s [new file with mode: 0644]
llvm/test/MC/RISCV/rv32xtheadmac-valid.s [new file with mode: 0644]
llvm/test/MC/RISCV/rv64xtheadmac-valid.s [new file with mode: 0644]
llvm/test/MC/RISCV/xtheadmac-invalid.s [new file with mode: 0644]