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(parent: 51d8095) | patch
riscv: Implement non-coherent DMA support via SiFive cache flushing
authorEmil Renner Berthing <kernel@esmil.dk>
Sat, 12 Jun 2021 23:48:31 +0000 (16:48 -0700)
committerŁukasz Stelmach <l.stelmach@samsung.com>
Thu, 9 Feb 2023 18:48:09 +0000 (19:48 +0100)
commitd3fb34eb1d7dfb4422e3ccde7c71d9a31e12b1c0
treef73e876fd0ed28ebb07c5cd9908189afbc24889dtree | snapshot
parent51d8095b90f12bed5d25f3b4609f8991044cc94ecommit | diff
riscv: Implement non-coherent DMA support via SiFive cache flushing

This variant is used on the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
arch/riscv/Kconfig diff | blob | history
arch/riscv/mm/dma-noncoherent.c diff | blob | history
Domain: System / Kernel;