Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and 'clk-imx...

Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and 'clk-imx' into clk-next

 - Convert ux500 to clk_hw
 - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
 - MediaTek MT8186 SoC clk support
 - Move MediaTek driver to clk_hw provider APIs

* clk-ux500:
  clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base()
  clk: ux500: Implement the missing CLKOUT clocks
  clk: ux500: Rewrite PRCMU clocks to use clk_hw_*
  clk: ux500: Drop .is_prepared state from PRCMU clocks
  clk: ux500: Drop .is_enabled state from PRCMU clocks
  dt-bindings: clock: u8500: Add clkout clock bindings

* clk-mtk: (22 commits)
  clk: mediatek: mt8173: Switch to clk_hw provider APIs
  clk: mediatek: Switch to clk_hw provider APIs
  clk: mediatek: Replace 'struct clk' with 'struct clk_hw'
  clk: mediatek: apmixed: Drop error message from clk_register() failure
  clk: mediatek: Make mtk_clk_register_composite() static
  clk: mediatek: use en_mask as a pure div_en_mask
  clk: mediatek: update compatible string for MT7986 ethsys
  clk: mediatek: Add MT8186 ipesys clock support
  clk: mediatek: Add MT8186 mdpsys clock support
  clk: mediatek: Add MT8186 camsys clock support
  clk: mediatek: Add MT8186 vencsys clock support
  clk: mediatek: Add MT8186 vdecsys clock support
  clk: mediatek: Add MT8186 imgsys clock support
  clk: mediatek: Add MT8186 wpesys clock support
  clk: mediatek: Add MT8186 mmsys clock support
  clk: mediatek: Add MT8186 mfgsys clock support
  clk: mediatek: Add MT8186 imp i2c wrapper clock support
  clk: mediatek: Add MT8186 apmixedsys clock support
  clk: mediatek: Add MT8186 infrastructure clock support
  clk: mediatek: Add MT8186 topckgen clock support
  ...

* clk-tegra:
  clk: tegra: Update kerneldoc to match prototypes
  clk: tegra: Replace .round_rate() with .determine_rate()
  clk: tegra: Register clocks from root to leaf
  clk: tegra: Add missing reset deassertion

* clk-allwinner:
  clk: sunxi-ng: h616: Add PLL derived 32KHz clock
  clk: sunxi-ng: h6-r: Add RTC gate clock

* clk-imx:
  clk: imx8mp: fix usb_root_clk parent
  clk: imx8mp: add clkout1/2 support
  clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
  clk: imx8mp: Add DISP2 pixel clock
  clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu()
  clk: imx: Add check for kcalloc
  clk: imx8mn: add GPT support
  dt-bindings: imx: add clock bindings for i.MX8MN GPT
  clk: imx: Remove the snvs clock
  clk: imx8m: check mcore_booted before register clk
  clk: imx: add mcore_booted module paratemter
  clk: imx8mq: add 27m phy pll ref clock