clk: qcom: gdsc: Fix the handling of PWRSTS_RET support
authorRajendra Nayak <quic_rjendra@quicinc.com>
Tue, 20 Sep 2022 11:15:15 +0000 (16:45 +0530)
committerBjorn Andersson <andersson@kernel.org>
Wed, 28 Sep 2022 02:58:38 +0000 (21:58 -0500)
commitd399723950c45cd9507aef848771826afc3f69b0
treea96da373239c0e427cf2aa03fabc8ab9c007f318
parente55d937d8cf391c1fb9afad296948b3697ad96f7
clk: qcom: gdsc: Fix the handling of PWRSTS_RET support

GDSCs cannot be transitioned into a Retention state in SW.
When either the RETAIN_MEM bit, or both the RETAIN_MEM and
RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW
takes care of retaining the memory/logic for the domain when
the parent domain transitions to power collapse/power off state.

On some platforms where the parent domains lowest power state
itself is Retention, just leaving the GDSC in ON (without any
RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition
it to Retention.

The existing logic handling the PWRSTS_RET seems to set the
RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified
but then explicitly turns the GDSC OFF as part of _gdsc_disable().
Fix that by leaving the GDSC in ON state.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220920111517.10407-1-quic_rjendra@quicinc.com
drivers/clk/qcom/gdsc.c
drivers/clk/qcom/gdsc.h