[TableGen] Emit table mapping physical registers to base classes
authorCarl Ritson <carl.ritson@amd.com>
Tue, 20 Dec 2022 06:21:51 +0000 (15:21 +0900)
committerCarl Ritson <carl.ritson@amd.com>
Tue, 20 Dec 2022 06:22:28 +0000 (15:22 +0900)
commitd393d0d24239aedfd3c8166e7dc188f360104cac
tree8b1553882c1b9f4b7a67c4ebb883fb7d5a9b9b70
parente4377cdde60bf9cf0267445f80a97cfaf9d5aacf
[TableGen] Emit table mapping physical registers to base classes

Allow targets to define a mapping from registers to register
classes such that each register has exactly one base class.
As registers may be in multiple register classes the base class
is determined by the container class with the lowest BaseClassOrder.

Only register classes with BaseClassOrder set are considered
when determining the base classes.  By default BaseClassOrder is
unset in RegisterClass so no code is generated unless a target
explicit defines one or more base register classes.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D139616
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/include/llvm/Target/Target.td
llvm/test/TableGen/RegisterInfoEmitter-BaseClassOrder.td [new file with mode: 0644]
llvm/utils/TableGen/CodeGenRegisters.h
llvm/utils/TableGen/RegisterInfoEmitter.cpp