review.tizen.org Git - platform/upstream/llvm.git/commit

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author	Simon Pilgrim <llvm-dev@redking.me.uk>
	Sun, 7 Nov 2021 15:06:54 +0000 (15:06 +0000)
committer	Simon Pilgrim <llvm-dev@redking.me.uk>
	Sun, 7 Nov 2021 15:06:54 +0000 (15:06 +0000)
commit	d391e4fe841d4289137b6cb1463fce2d1853a5eb
tree	2555bc2f0ca0f56464a26568d107d795943aeb25	tree \| snapshot
parent	9b8b16457c23c52b1eeef600cb65a2d160041433	commit \| diff

[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth.

Helps prevent future scheduler model mismatches like those that were only addressed in D44687.

Differential Revision: https://reviews.llvm.org/D113302

301 files changed:

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ExpandPseudo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86FastISel.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86IndirectThunks.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstrControl.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86MCInstLower.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86RegisterInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86SchedBroadwell.td		diff \| blob \| history
llvm/lib/Target/X86/X86SchedHaswell.td		diff \| blob \| history
llvm/lib/Target/X86/X86SchedIceLake.td		diff \| blob \| history
llvm/lib/Target/X86/X86SchedSandyBridge.td		diff \| blob \| history
llvm/lib/Target/X86/X86SchedSkylakeClient.td		diff \| blob \| history
llvm/lib/Target/X86/X86SchedSkylakeServer.td		diff \| blob \| history
llvm/lib/Target/X86/X86ScheduleAtom.td		diff \| blob \| history
llvm/lib/Target/X86/X86ScheduleZnver1.td		diff \| blob \| history
llvm/lib/Target/X86/X86ScheduleZnver2.td		diff \| blob \| history
llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/auto-successor.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/block-address-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/branch-probabilities.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/callee-saved-info.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/cfi-offset.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/constant-pool.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/constant-value-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/dbg-value-list.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/dead-register-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-stack-object.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/function-liveins.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/global-value-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/immediate-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/jump-table-info.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/killed-register-flag.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/large-index-number-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/machine-instructions.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/machine-verifier.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/newline-handling.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/roundtrip.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/standalone-register-error.mir		diff \| blob \| history
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llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/undef-register-flag.mir		diff \| blob \| history
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llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp		diff \| blob \| history

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