PCI: Workaround for Intel MPS errata
authorJon Mason <mason@myri.com>
Fri, 14 Oct 2011 19:56:13 +0000 (14:56 -0500)
committerJesse Barnes <jbarnes@virtuousgeek.org>
Thu, 27 Oct 2011 19:45:42 +0000 (12:45 -0700)
commitd387a8d66670371e6be3b6d6bde2e38b8cade076
tree988a0d0898779694f4299886d7b72607a5b4fdea
parent086ac11f6435c9dc2fe5025fc8ea3a1dbca273d6
PCI: Workaround for Intel MPS errata

Intel 5000 and 5100 series memory controllers have a known issue if read
completion coalescing is enabled and the PCI-E Maximum Payload Size is
set to 256B.  To work around this issue, disable read completion
coalescing in the memory controller and root complexes.  Unfortunately,
it must always be disabled, even if no 256B MPS devices are present, due
to the possibility of one being hotplugged.

Links to erratas:
http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf
http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf

Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into
the problem.

Tested-and-Reported-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
drivers/pci/quirks.c