drm/i915/display/dp: Compute the correct slice count for VDSC on DP
authorManasi Navare <manasi.d.navare@intel.com>
Fri, 4 Dec 2020 20:58:04 +0000 (12:58 -0800)
committerManasi Navare <manasi.d.navare@intel.com>
Tue, 8 Dec 2020 01:47:13 +0000 (17:47 -0800)
commitd371d6ea92ad2a47f42bbcaa786ee5f6069c9c14
treecfaf2da41a6b12f54d307fd72cc00a9e1909b375
parent4b970408dbc9ce9a5a6e2e8b5a478199b471c7fe
drm/i915/display/dp: Compute the correct slice count for VDSC on DP

This patch fixes the slice count computation algorithm
for calculating the slice count based on Peak pixel rate
and the max slice width allowed on the DSC engines.
We need to ensure slice count > min slice count req
as per DP spec based on peak pixel rate and that it is
greater than min slice count based on the max slice width
advertised by DPCD. So use max of these two.
In the prev patch we were using min of these 2 causing it
to violate the max slice width limitation causing a blank
screen on 8K@60.

Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201204205804.25225-1-manasi.d.navare@intel.com
drivers/gpu/drm/i915/display/intel_dp.c