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(parent: 4a3e69d) | patch
correct L3 cache settings for baytrail
authorGuo Yejun <yejun.guo@intel.com>
Thu, 22 May 2014 17:24:20 +0000 (01:24 +0800)
committerZhigang Gong <zhigang.gong@intel.com>
Fri, 23 May 2014 03:07:32 +0000 (11:07 +0800)
commitd365c54253050dd280b79250c3e9e0ed0da324a8
tree915831ee8db1b90e602b45c004e8b491ac34cd4ftree | snapshot
parent4a3e69d6df6141777dd67e97aff2a451bc01aa00commit | diff
correct L3 cache settings for baytrail

baytrail and ivb have different register bits layout for L3 cache,
so, add a special path for baytrail.

Signed-off-by: Guo Yejun <yejun.guo@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Reviewed-bu: "Song, Ruiling" <ruiling.song@intel.com>
src/intel/intel_gpgpu.c diff | blob | history
Domain: SCM / Uncategorized;