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(parent: d2a3671) | patch
clk: hi3660: fix incorrect uart3 clock freqency
authorZhong Kaihua <zhongkaihua@huawei.com>
Mon, 7 Aug 2017 14:51:56 +0000 (22:51 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 14 Nov 2017 17:48:59 +0000 (09:48 -0800)
commitd33fb1b9f0fcb67f2b9f8b1891465a088a9480f8
tree3cbf8228d5ff1de69e50ed66726e281e0ecabb86tree | snapshot
parentd2a3671ebe6479483a12f94fcca63c058d95ad64commit | diff
clk: hi3660: fix incorrect uart3 clock freqency

UART3 clock rate is doubled in previous commit.

This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.

This patch changes clock source rate of clk_factor_uart3 to 100000000.

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/hisilicon/clk-hi3660.c diff | blob | history
Domain: System / Kernel;