gpadc: prevent CPU from S0i3 when ADC is active

gpadc: prevent CPU from S0i3 when ADC is active

Under the following scenario:
	1. IPC1 request sent to SCU
	2. PM_CMD s0ix entry request sent to SCU
	3. MWAIT C6 abort (or no attempt at MWAIT C6)
	If steps #1 an #2 are sufficiently close (maybe within 200us) there is
a possibility that SCU will handle the PM_CMD first and begin waiting on an
ack_c6 response from the MWAIT that is expected. Since the MWAIT never comes
(or is aborted) SCU will have to eventually time out before being able to move
on and handle the IPC1 request.

Change-Id: I00674d66806d127cef0810fa023eed5dd0fda7c2
Signed-off-by: Bin Yang <bin.yang@intel.com>
[ port to new pm_qos_add_request() interface -Guanqun ]
Signed-off-by: Lu Guanqun <guanqun.lu@intel.com>