Merge branch 'CR_863_UART_yanhong.wang' into 'jh7110_fpga_dev_5.15'
authorandy.hu <andy.hu@starfivetech.com>
Sun, 24 Apr 2022 03:48:10 +0000 (03:48 +0000)
committerandy.hu <andy.hu@starfivetech.com>
Sun, 24 Apr 2022 03:48:10 +0000 (03:48 +0000)
commitd2c8a774f26b8ca0a58920a5b8541efddb10ae21
treeda89d6752d5eb658f5df96f0dcb1f7667217020f
parent159b6d3671106a6ee99c9acfcd8e64799a4b509e
parent3a5b1998599af0477dc9137be2fad96f90a996d1
Merge branch 'CR_863_UART_yanhong.wang' into 'jh7110_fpga_dev_5.15'

dt-bingings:uart:jh7110: add clks and reset signals to uarts

See merge request sdk/sft-riscvpi-linux-5.10!21