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(parent: dc70c56) | patch
[RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.
authorCraig Topper <craig.topper@sifive.com>
Sat, 23 Jan 2021 22:41:42 +0000 (14:41 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sat, 23 Jan 2021 23:08:18 +0000 (15:08 -0800)
commitd2927f786e877410d90c1e6f0e0c7d99524529c5
treed9a7a73a78a6163db28344f9fb357e7c62a7c1a0tree | snapshot
parentdc70c56be5922b874b1408edc1315fcda40680bacommit | diff
[RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.

We try to do this during DAG combine with SimplifyDemandedBits,
but it fails if there are multiple nodes using the AND. For
example, multiple shifts using the same shift amount.
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll diff | blob | history
llvm/test/CodeGen/RISCV/atomic-rmw.ll diff | blob | history
Domain: System / Toolchain;