GlobalISel: disambiguate types when printing MIR
authorTim Northover <tnorthover@apple.com>
Mon, 12 Sep 2016 11:20:10 +0000 (11:20 +0000)
committerTim Northover <tnorthover@apple.com>
Mon, 12 Sep 2016 11:20:10 +0000 (11:20 +0000)
commitd28d3cc079bbda0e0d028a1cd012db0f9d0bcff7
tree137a13971af516384119817ef02fd080d8c3a546
parentc6a123111a3b24ea48d15c13b4374c3671fea815
GlobalISel: disambiguate types when printing MIR

Some generic instructions have multiple types. While in theory these always be
discovered by inspecting the single definition of each generic vreg, in
practice those definitions won't always be local and traipsing through a big
function to find them will not be fun.

So this changes MIRPrinter to print out the type of uses as well as defs, if
they're known to be different or not known to be the same.

On the parsing side, we're a little more flexible: provided each register is
given a type in at least one place it's mentioned (and all types are
consistent) we accept the MIR. This doesn't introduce ambiguity but makes
writing tests manually a bit less painful.

llvm-svn: 281204
13 files changed:
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir