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[RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector
authorLuke <luke957@foxmail.com>
Fri, 26 Feb 2021 14:10:30 +0000 (22:10 +0800)
committerLuke <luke957@foxmail.com>
Fri, 5 Mar 2021 02:54:51 +0000 (10:54 +0800)
commitd28297ff68eeecc381426416ff92a466953cd93d
tree3e62834fa03bbec180904cf940eda36f57248ed5tree | snapshot
parent2357d29335f293ac0333dd86a0118856d586922fcommit | diff
[RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector

By implementing the method "unsigned RISCVTTIImpl::getRegisterBitWidth(bool Vector)",
fixed-length vectorization is enabled when possible. Without this method, the
"#pragma clang loop" directive is needed to enable vectorization(or the cost model
may inform LLVM that "Vectorization is possible but not beneficial").

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97549
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h diff | blob | history
llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll [new file with mode: 0644] blob
Domain: System / Toolchain;