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(parent: 45e8ba8) | patch
[x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433)
authorSanjay Patel <spatel@rotateright.com>
Mon, 3 Oct 2016 16:38:27 +0000 (16:38 +0000)
committerSanjay Patel <spatel@rotateright.com>
Mon, 3 Oct 2016 16:38:27 +0000 (16:38 +0000)
commitd27a21874b3d83bf0695eea90b6ba5aa3f600c88
treebbfa396dbd061eac67dc4f9ecce1fd9c482b18bbtree | snapshot
parent45e8ba88c32bd929e024834f3f539f8bb8a94454commit | diff
[x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433)

This should fix:
https://llvm.org/bugs/show_bug.cgi?id=30433

There are a couple of open questions about the codegen:
1. Should we let scalar ops be scalars and avoid vector constant loads/splats?
2. Should we have a pass to combine constants such as the inverted pair that we have here?

Differential Revision: https://reviews.llvm.org/D25165

llvm-svn: 283119
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/Analysis/CostModel/X86/arith-fp.ll diff | blob | history
llvm/test/CodeGen/X86/vec-copysign.ll diff | blob | history
llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll diff | blob | history
Domain: System / Toolchain;